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Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Lead-Free Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current
HEXFET Power MOSFET
IRLR7821PBF IRLU7821PbF (R)
Qg
10nC 10m:
PD - 95091B
VDSS RDS(on) max
30V
D-Pak I-Pak IRLR7821PBF IRLU7821PbF
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TC = 100C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
30 20 65f 47f 260 75 37.5 0.50 -55 to + 175
Units
V
A
Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range
W W/C C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB Mount)gA Junction-to-Ambient
Typ.
--- --- ---
Max.
2.0 50 110
Units
C/W
Notes through are on page 11
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10/02/06
IRLR/U7821PbF
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 --- --- --- 1.0 --- --- --- --- --- 46 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 23 7.5 9.5 --- -5.3 --- --- --- --- --- 10 2.0 1.2 2.5 4.3 3.7 8.5 11 4.2 10 3.2 1030 360 120 --- --- 10 12.5 --- --- 1.0 150 100 -100 --- 14 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 15V ns nC nC VDS = 16V VGS = 4.5V ID = 12A S nA V mV/C A V
Conditions
VGS = 0V, ID = 250A
mV/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 15A VGS = 4.5V, ID = 12A
f f
VDS = VGS, ID = 250A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID = 12A
See Fig. 16 VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 12A Clamped Inductive Load
f
= 1.0MHz
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energydh Avalanche CurrentA Repetitive Avalanche Energy Typ. --- --- --- Max. 230 12 7.5 Units mJ A mJ
--- --- --- --- --- --- --- --- 26 15
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ah Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
65f A 260 1.0 38 23 V ns nC
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. TJ = 25C, IS = 12A, VGS = 0V TJ = 25C, IF = 12A, VDD = 15V di/dt = 100A/s
f
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRLR/U7821PbF
10000
TOP VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V
1000
TOP VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V
ID, Drain-to-Source Current (A)
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
100
BOTTOM
10
10
2.5V 20s PULSE WIDTH Tj = 175C
1 0.1 1 10 100
1
2.5V 20s PULSE WIDTH Tj = 25C
0.1 1 10 100
0.1
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
I D = 65A
100
T = 175 J
C
R DS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)
1.5
(Normalized)
1.0
10
0.5
TJ = 25
C V DS= 15V 20s PULSE WIDTH
1 2.0 4.0 6.0
8.0
10.0
0.0 -60 -40 -20 0 20 40 60 80
V GS = 10V
100 120 140 160 180
V GS Gate-to-Source Voltage (V) ,
TJ, Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRLR/U7821PbF
10000 VGS = 0V, f = 1 MHZ Ciss = C + C , C SHORTED gs gd ds Crss = C gd Coss = Cds + Cgd
6
VGS , Gate-to-Source Voltage (V)
ID= 12A
5 4 3 2 1 0
VDS= 24V VDS= 16V
C, Capacitance(pF)
1000
Ciss Coss Crss
100
10 1 10 100
0
2
4
6
8
10
12
VDS, Drain-to-Source Voltage (V)
Q G Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED BY R DS(on)
100
ID, Drain-to-Source Current (A)
100 100sec 10 1msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 VDS, Drain-to-Source Voltage (V) 10msec
I SD , Reverse Drain Current (A)
TJ = 175 C
10
1
T J= 25 C
0.1 0.0 0.5 1.0
V GS = 0 V
1.5 2.0
100
V SD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLR/U7821PbF
70
2.5
60
VGS(th) Gate threshold Voltage (V)
LIMITED BY PACKAGE
2.0
50
I D , Drain Current (A)
40
ID = 250A
1.5
30
20
1.0
10
0 25 50 75 100 125 150 175
0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200
TC , Case Temperature ( C)
T J , Temperature ( C )
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
10
(Z thJC )
1
D = 0.50
0.20
Thermal Response
0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t 2 +T C 1
J = P DM x Z thJC
0.1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U7821PbF
15V
1000
TOP
VDS
L
DRIVER
800
BOTTOM
ID 4.9A 8.5A 12A
RG
20V VGS
D.U.T
IAS tp
+ V - DD
EAS , Single Pulse Avalanche Energy (mJ)
A
600
0.01
400
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
200
0 25 50 75 100 125 150 175
Starting Tj, Junction Temperature
( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
VDS VGS RG
Current Regulator Same Type as D.U.T.
RD
Fig 12b. Unclamped Inductive Waveforms
D.U.T.
+
-V DD
V GS
Pulse Width 1 s Duty Factor 0.1 %
50K 12V .2F .3F
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS 90%
VGS
3mA
IG
ID
10% VGS
td(on) tr t d(off) tf
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRLR/U7821PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRLR/U7821PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* Ploss = Pconduction + P + Poutput drive
Ploss = Irms x Rds(on)
+ ( g x Vg x f ) Q
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1.
Ploss = (Irms 2 x Rds(on ) ) Qgd +I x x Vin x ig + (Qg x Vg x f ) + Qoss x Vin x f 2 Qgs 2 f + I x x Vin x f ig
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRLR/U7821PbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPL E: T HIS IS AN IRF R120 WIT H AS S EMBLY LOT CODE 1234 AS S EMB LED ON WW 16, 2001 IN T HE AS S EMBLY LINE "A" Note: "P" in as s embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBL Y LOT CODE PART NUMBER
IRFR120 12 116A 34
DAT E CODE YEAR 1 = 2001 WEEK 16 L INE A
OR
INT ERNAT IONAL RECT IF IER L OGO AS S EMBLY L OT CODE PART NUMBER
IRF R120 12 34
DAT E CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPT IONAL) YEAR 1 = 2001 WEEK 16 A = AS S EMBL Y S IT E CODE
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IRLR/U7821PbF
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Package Outline
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: THIS IS AN IRFU120 WIT H AS SEMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 2001 IN THE AS S EMBLY LINE "A" Note: "P" in ass embly line position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 119A 56 78
DATE CODE YEAR 1 = 2001 WEEK 19 LINE A
OR
INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 56 78
DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 1 = 2001 WEEK 19 A = AS S EMBLY S ITE CODE
10
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IRLR/U7821PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. Starting TJ = 25C, L = 3.2mH RG = 25, IAS = 12A. Pulse width 400s; duty cycle 2%.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.10/2006
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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